1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device, in which a dummy gate part is formed in a peripheral region, and a method of fabricating the same.
2. Description of the Related Art
As semiconductor devices continue to be more densely integrated, individual circuit patterns are becoming more densely arranged to attempt to include more semiconductor devices within the same area. The high density of circuit patterns causes various problems during manufacturing of semiconductor devices, and thus new methods of manufacturing semiconductor devices are being developed.
Generally, in the manufacture of a semiconductor device, a gate pattern is formed on a semiconductor substrate, an interlayer insulation layer is formed on the gate pattern, and a circuit layer is formed on the interlayer insulation layer. To form the circuit layer on an even interlayer insulation layer, chemical mechanical polishing (CMP) is performed on the interlayer insulation layer after the interlayer insulation layer is formed. However, due to the formation of gate patterns in a cell region, the interlayer insulation layer will not be level with a peripheral region even after CMP. If a pattern corresponding to the circuit pattern is formed on the interlayer insulation layer, it may cause a defective pattern due to the lack of a defocus margin.
Therefore, a dummy gate part is formed in the peripheral region, which corresponds to a real gate parts in the cell region, to prevent the aforementioned problem.
FIGS. 1 through 3 are sectional views illustrating a manufacturing process of a semiconductor device having a dummy gate part of the prior art.
Referring to FIG. 1, the top surface of a semiconductor device 10 is divided into two regions: a cell region C having formed thereon semiconductor memory devices and a peripheral region P formed around the cell region C and having formed thereon some control devices and dummy devices. In the cell region C, a real active region 11a is formed, surrounded and defined by a device isolating region 12. Also, a plurality of dummy active regions 11c, surrounded and defined by the device isolating region 12, and some real active regions 11b are formed. Also, a plurality of real gate parts 14a, which form semiconductor devices, are formed on the semiconductor substrate 10 in the cell region C by having a gate insulation layer (not shown) therebetween. A plurality of dummy gate parts 14c are also formed on the semiconductor substrate 10 in the peripheral region P by having a gate insulation layer (not shown) there-between. As needed, some real gate parts 14b may also be formed on the semiconductor substrate 10 in the peripheral region P.
The dummy gate parts 14c formed in the peripheral region P are formed in correspondence to the real gate parts 14a only to decrease a difference in height between upper surfaces of the cell region C and the peripheral region P (herein referred to as “a level difference”), and are insulated from surrounding conductive layers by a insulating material layer. Also, each of the dummy gate parts 14c is formed on each of the dummy active regions 11c, respectively. When impurity ions are implanted to the real active region 11a in the cell region C, the impurity ions may also be undesirably implanted to the dummy active regions 11c in the peripheral region P, and thus the dummy gate parts 14c are formed so that each dummy gate part 14c covers a corresponding dummy active region 11c. 
Referring to FIG. 2, a thick interlayer insulation layer 16 is formed on the semiconductor substrate 10, on which the real gate parts 14a and the dummy gate parts 14c are formed. While the interlayer insulation layer 16 in the cell region C is evenly formed due to high density of the real gate parts 14a, the interlayer insulation layer 16 in the peripheral region P is formed unevenly because relatively more of the material forming the interlayer insulation layer fills spaces between the dummy gate parts 14c, formed at a density lower than that of the real gate parts 14a. Thus, there may be many sunken parts on the surface of the interlayer insulation layer 16 in the peripheral region P.
Referring to FIG. 3, CMP is performed on the interlayer insulation layer 16 to form an even top surface. Since the density of the real gate parts 14a in the cell region C is larger than the density of the dummy gate parts 14c in the peripheral region P, a level difference t at right side is created.
Therefore, a circuit layer or another interlayer insulation layer (not shown), which is to be formed on the interlayer insulation layer, cannot be formed evenly due to the level difference t between the cell region C and the peripheral region P, and thus the unevenness may cause a defective pattern in the formation of circuit patterns.